1. Field of the Invention
The present invention relates to digital circuitry for computing devices. In particular, the present invention relates to adjusting power consumption of digital circuitry by generating a frequency error representing error in propagation delay.
2. Description of the Prior Art
Reducing power consumption of digital circuitry in computing devices increases battery life in portable applications (such as cellular telephones, portable computers, digital cameras, and the like) in addition to increasing the overall reliability/longevity since reducing power consumption reduces the operating temperature and associated stress on the device. In some computing devices, the propagation delays through certain critical paths of the digital circuitry that must remain within prescribed thresholds for proper operation affect the power consumption of the device. For example, manufactures have imposed certain restrictions on process tolerances and supply voltages to ensure the propagation delays remain within an acceptable operating range under worst case operating conditions, such as worst-case process deviation and highest ambient temperature. However, operating all of the computing devices at a predetermined supply voltage to account for worst case conditions leads to inefficient power consumption for the majority of the devices that could operate with acceptable performance using a lower supply voltage.
An alternative approach to achieving acceptable propagation delays is to limit the clocking frequency of the digital circuitry to ensure reliable performance under all operating conditions, such as process deviations and ambient temperature. Reducing the clocking frequency also reduces power consumption, which is directly related to the switching frequency of the digital circuitry. However, for applications where limiting the clocking frequency leads to unacceptably slow performance, acceptable propagation delay is achieved by increasing the supply voltage.
Prior art techniques have been suggested for measuring the propagation delay through a critical path of the digital circuitry in order to adapt the supply voltage and/or the clocking frequency in order to optimize the power consumption and/or operating speed of each individual device. FIG. 1 shows an overview of a typical prior art implementation for measuring the propagation delay of a critical path circuit 2 and adjusting the supply voltage and/or clock frequency 4 (see, for example, U.S. Pat. Nos. 6,157,247 and 6,535,735). Matched delay circuit 6 is included in the device, which matches the operating characteristics of the critical path circuit 2. A periodic input signal 8 is applied to the matched delay circuit 6, wherein the output 10 of the matched delay circuit 6 is the periodic input signal 8 shifted by a phase proportional to the propagation delay of the critical path circuit 2. A phase comparator 12 measures the phase difference between the periodic input signal 8 and the output 10 of the matched delay circuit 6, wherein the phase difference generates a pulse width modulated (PWM) signal 14 having a duty cycle proportional to the propagation delay of the matched delay circuit 6. The PWM signal 14 is converted by conversion circuitry 16 into an analog signal 18 which is filtered by filter 20. The output of filter 20 is a DC control signal 22 applied to an adjustable supply voltage/clock circuit 24 which outputs the adjusted supply voltage and/or clock frequency 4 applied to both the critical path circuit 2 and the matched delay circuit 2. In this manner, the supply voltage and/or clock frequency 4 is adjusted to maintain a target propagation delay through the critical path circuit 2 thereby adapting the power consumption and/or operating speed of the device.
There are a number of drawbacks with the prior art phase comparison technique for measuring the error in propagation delay in order to adjust the supply voltage and/or clocking frequency of digital circuits. In the above mentioned '247 patent, the target propagation delay is set equal to the period of the input signal 8 so that the supply voltage is adjusted until the output of the phase comparator is zero (i.e., the supply voltage is adjusted until the output 10 of the matched delay circuit 6 is delayed by one period of the input signal 8). This technique requires the input signal 8 be generated with a period equal to the target propagation delay resulting in design limitations, for example, if the critical path changes relative to the mode of operation or if there are two critical paths with different propagation delays operating simultaneously. Additional margin (in the form of higher supply voltage or lower clocking frequency) is also required to compensate for tolerances in converting 16 the PWM signal 14 into the analog signal 18. That is, a zero phase error in the PWM signal 14 will not convert 16 exactly to a zero analog signal 18, and vise versa, leading to an offset in the propagation delay error. For example, since the DC control signal 22 is proportional to the input frequency 8, as well as proportional to the voltage supplying the conversion circuitry 16, and since the PWM signal frequency is comparable to the delays through the digital circuit, the proportionality of voltage to frequency is not precise. Output rise and fall time errors, impedance, differential delays of the circuitry between rise and fall times, and so forth, all contribute errors in the proportionality constant, and add voltage conversion offsets. As the target propagation delay through the critical path circuit 2 decreases for higher performance circuits, the delay gets closer to the operating speeds of the digital gates and the proportionality and offset problems are magnified. Since the highest performance circuits (which require minimal gate delays) consume the most power, the benefit of optimizing power consumption is even more apparent, yet the conversion errors are at their worst for these circuits because the frequency needed to measure the propagation delay is closest to the gate speed limits.
In the above mentioned '735 patent, the propagation delay error is measured as the difference between the DC control signal 22 and a reference signal (e.g., a reference voltage). However similar to the '247 patent, the conversion circuitry 16 for converting the PWM signal 14 into the analog signal 18 exhibits unavoidable tolerances requiring additional margin. Moreover, the reference signal for comparing against the DC control signal 22 has tolerances, as does the comparison circuitry. Still further, if the clocking frequency of the digital circuitry is adjusted (e.g., to facilitate different operating modes or to optimize power consumption), non-linearities between the frequency of the input signal 8 and the target reference signal leads to additional voltage errors. Since power and speed are proportional to the square of the supply voltage of a digital circuit, these introduced voltage errors multiply the power and speed error significantly.
Yet another drawback with the '735 patent is that the period of the input signal 8 must be appropriately selected relative to the propagation delay of the critical path circuit 2 so that the phase shift at the output 10 of the matched delay circuit 6 has sufficient range while timely updating the output of the phase comparator 12. This problem is exacerbated if a device has a number of critical path circuits that may be enabled at different times, wherein the propagation delay varies significantly between each critical path circuit requiring a corresponding change in the periodic input signal 8. If two such critical paths exist and must operate simultaneously, for example, and the delay through each circuit differs substantially, then either input signals 8 with different frequencies must be provided, or different reference signals to compare against the DC control signal 22 must be used, requiring additional circuitry. Further, the worst critical path must be determined before the circuit is manufactured, so that when both circuits operate the correct circuit is measured for control of the voltage loop requiring additional margin when multiple circuits run simultaneously.
Still further, a control loop implemented with the prior art phase comparison technique exhibits poor transient response requiring additional margin to ensure proper operation of the device under all operating conditions. The voltage control loop is typically tuned for the highest possible gain within stability limits to achieve the best transient response. Lower frequency response is required to allow for the performance differences that will occur due to the above-mentioned proportionality differences (which translate into a gain change in the control loop). This lower frequency response means the loop must be tuned for slower transient response, which in turn requires either larger energy storage elements to limit the voltage droop, or larger margins to allow for a larger supply voltage transient drop. More importantly, the loop response will vary with each part produced.
There is, therefore, a need to improve upon the current techniques for adjusting the supply voltage and/or clocking frequency of critical path circuitry in order to optimize power consumption and/or operating speed of computing devices, such as cellular telephones, portable computers, digital cameras, and the like.